Key Features
Interfaces
- Full-duplex 10/100/1000 Mbps Ethernet interfaces
- Configurable for up to 32 ports
- MII/RMII/GMII/RGMII/SGMII/QSGMII Physical Layer device (PHY) interfaces
- Different data rates supported for each port
Switching
- Non-blocking matrix architecture, 100% data through-put for GbE traffic
- Dynamic MAC table with automatic MAC addresses learning and aging - up to 4096 entries
- Static MAC table - up to 4096 entries
- Time-Aware Shaper
- Jumbo Frame Management
- Broadcast / Multicase Storm Protection
- Per-Port Rate limiting - Broadcast, Unicast and Multicast traffic
- Port-Based VLAN support
Configuration
- MDIO, UART, AXI4-lite or CoE management interfaces
- Configuration over Ethernet (CoE): Full access to internal registers through the same Ethernet link that connects to the CPU
- Driver packages provided with MTSNSwitch IP Cores
Time-Sensitive Networking
- IEEE 802.1AS(rev) for Time Synchronization Layer
- IEEE 802.1Qav for Reserved Traffic
- Credit Based Shaper: Configurable bandwidth reservation for each traffic class
- IEEE 802.1Qbv for Scheduled Traffic
- Time Aware Shaper: Configurable number of time slots
- IEEE 802.1Qcc for Network Management
- RESTCONF for managing YANG data
- NETCONF for managing YANG data
- IEEE 802.1Qci for Stream Filtering and Policing
- IEEE 802.1AB for LLDP (Link Layer Discovery Protocol)
- IEEE 802.1w for Rapid Spanning Tree Protocol
- IEEE 802.1s for Multiple Spanning Tree Protocol (*)
- IEEE 802.1CB for Frame Replication and Elimination for Reliability
- Cut-Through support for Isochronous Scheduled Traffic (*)
- IEEE 802.1Qbu/802.3br for Frame Preemption
Low Level Configuration
- MDIO, UART, AXI4-lite or CoE management interfaces
- Configuration-over-Ethernet (CoE): Full access to internal registers through the same Ethernet link that connects to the CPU
- Drivers are provided with IP Core purchase
High Level Configuration
- RESTCONF/NETCONF YANG model support (CNC configuration)
- High-level Configuration GUI
* Future Release and/or Interoperability Test pending
SoC-e Multiport TSN solutions
Multiport TSN development kits and IP Cores
Introduction
Time-Sensitive-Networking (TSN) delivers real-time Ethernet capabilities including guaranteed bandwidth and deterministic latency.
TSN is the name of the IEEE 802.1 Task Group responsible for standards at the Data Link Layer. This governs the specifications for time-synchronisation and ultra-low-latency streaming services through IEEE 802 networks.
These Multiport TSN (MTSN) solutions allow Real-Time traffic and Best-Effort traffic to co-exist in a single Ethernet Network.
Recab UK are working with SoC-e because they are world-leaders in FPGA based Ethernet solutions and offer the most comprehensive TSN features and functions support, through their FPGA based approach. Many organisations, using older deterministic protocols today, such as MIL-1553B, CAN, HDLC and IRIG-B are looking towards TSN for future deployments. There is also significant momentum behind safety-critical (SIL) implementations of TSN, which SoC-e are working in through their research and development teams.
These multiport TSN (MTSN) development kits are aimed at experienced networking engineers who are interested in testing, researching, implementing and deploying multiport TSN solutions in their applications. The kits are intended for use in a lab or development office setting. We will be happy to discuss ways to use the equipment in other environments.
The SoC-e MTSN IP Cores offer a deployable, long-life and highly configurable software solution that takes the theory developed in the lab on these MTSN kits out into the field. SoC-e MTSNSwitch IP cores are supported on XIlinx 7-Series (Zynq recommended), Ultrascale and Ultrascale+ Zynq MPSoC FPGA devices.